Tamworth

Invotec Tamworth

Dedicated to precision & reliability, and offers a broad range of high-specification PCB solutions.

Invotec Tamworth has the capability to manage a vast array of leading-edge materials and technologies which have been developed in partnership with our customers to deliver optimum performance under extreme conditions.

We excel in the defence and aerospace environments where reliability, quality, consistency and budgetary requirements are paramount. Invotec Tamworth is fully accredited by US MIL Spec.

Whilst we develop & manufacture products for some of the worlds biggest names in military and avionics markets, other core industry sectors include medical systems, telecommunications and security.

Unrivalled technical capabilities coupled with innovation and close customer and supplier relationships ensure a comprehensive and competitive service-backed offering.

Capability
  • Extensive range of technical capabilities
  • MIL Spec approved
  • Offers a vast range of advanced materials
  • HDI, thermal management, RF, Zo, etc
  • Advanced flex and flex-rigid product offering
  • Military, aerospace and high reliability market specialists
summary technology roadmap units current production capability current prototype planned production capability planned prototype
GENERAL
leadtime availability days 5 - 30 3 - 20 3 - 20 2 - 15

 

summary technology roadmap units

current production capability

 current prototype planned production capability planned prototype
BUILD / CONSTRUCTION
materials (type - FR4, CEM3 etc) text
Tg (glass transition temp) max C 260 280 260 280
dielectric constant (at 1MHz) value 4.0 ~ 4.9 3.5 ~ 4.0 3.5 ~ 4.9 3.0 ~ 4.9
loss tangent (@MHz) value <0.025 <0.003 <0.025 <0.003
min specified prepreg thickness µm 50 50 50 50
max inter-layer prepreg thickness µm 700 700 700 700
blind and buried vias (Y/N) Y Y Y Y
microvia (laser) (Y/N) Y Y Y Y

 

summary technology roadmap units current production capability current prototype planned production capability planned prototype
PADS AND HOLES
through hole size (FHS) µm 150 150 150 100
blind/buried hole size (DHS) µm 150 100 100 75
plated through hole size tolerance (+/-) µm 75 50 50 50
non plated hole size tolerance (+/-) µm 50 25 50 25
hole positional tolerance µm 75 50 50 37
through hole pad size (inner) (assume tangency) µm DHS + 250 DHS + 200 DHS +200 DHS + 175
through hole pad size (outer) (assume tangency) µm DHS + 200 DHS + 150 DHS + 150 DHS + 125
blind/buried pad size µm DHS + 250 DHS + 200 DHS + 200 DHS + 175
pressfit hole tolerance (+/-) µm 50 50 50 50

 

summary technology roadmap units current production capability current prototype planned production capability planned prototype
MISCELLANEOUS
design text N N N N
buried capacitance TM (Y/N) N N N Y
embedded coaxial technology (patent pending) (Y/N) N N N Y
embedded resistance (Y/N) N Y N Y
bellcore compliance (Y/N) N N N N
heatsink (internal) (Y/N) Y Y Y Y
heatsink (external (Y/N) Y Y Y Y

 

summary technology roadmap units current production capability current prototype planned production capability planned prototype
PRODUCT DIMENSIONS
max PCB delivery unit (testable) mm 575 - 500 575 - 500 575 - 500 575 - 500
min PCB thickness mm 0.8 0.4 0.4 0.25
max PCB thickness mm 5.0 6.0 5.0 > 6.0
PCB thickness tolerance % 10 8 8 < 8
board flatness (%) % 0.7 0.5 0.5 0.5
max layer count value 28 30 30 30 >
aspect ratio (0.3mm hole 20um min CU) ratio 8:1 10:1 10:1 > 10:1

 

summary technology roadmap units current production capability current prototype planned production capability planned prototype
INNERLAYERS (print & etch)
minimum track width & spacing ['pitch'/2] µm 75 62 75 50
Cu foil thickness (min) µm 17 12 9 5
Cu foil thickness (max) µm 210 210 210 > 210
cores with imbalanced copper (Y/N) Y Y Y Y
min dielectric thickness [cores] µm 50 25 25 < 25
track width tolerance µm 25 12 12 10

 

summary technology roadmap units current production capability current prototype planned production capability planned prototype
MICROVIA
microvias 1 to 2 & n to [n - 1] (Y/N) Y Y Y Y
min microvia hole size (drilled) µm 125 100 100 75
min microvia pad size capture (outer) µm 250 200 200 150
min microvia pad size bounce (inner) µm 300 250 250 200
microvia: 1 to 3 and N to [n-2] (Y/N) N Y Y Y
microvia with buried vias layer 2 to [n-1] (Y/N) Y Y Y Y
microvia: sequential build up (Y/N) Y (stacked vias) Y (stacked vias) Y (stacked vias) Y (stacked vias)
microvia: filling of vias (plated Cu) (Y/N) Y Y Y Y

 

summary technology roadmap units current production capability current prototype planned production capability planned prototype
OUTERLAYER (plated layers)
min track width & gap T/G µm 100 75 75 63
Cu foil thickness (min) µm 8 8 8 5
Cu foil thickness (max) µm 210 > 210 210 > 210
track width tolerance µm 25 25 25 12

 

summary technology roadmap units current production capability current prototype planned production capability planned prototype
SOLDERMASK
type text Probimer 77 Various Probimer 77 Various
min clearance to copper (design) µm 63 32 32 25
min solder dam µm 75 50 50 50
min breakdown voltage V 500 > 500 500 > 500
min hardness (pencil hardness) H 6H 6H 6H 6H
LDI soldermask capability (Y/N) N Y Y Y

 

summary technology roadmap units current production capability current prototype planned production capability planned prototype
SURFACE FINISH
HASL (min thickness) µm 2 5 2 5
HASL (max thickness) µm 50 15 50 15
SnPb reflow (Y/N) Y Y Y Y
Electroless Ni/Immersion Au (Y/N) Y Y Y Y
Ni thickness (min)
 µm 4 4 4 4
Ni thickness (max)
 µm 7 7 7 7
Au thickness (min)
 µm 0.05 0.05 0.05 0.05
Au thickness (max)
 µm 0.1 0.1 0.1 0.1
Electrolytic Ni/Au Y/N Y Y Y Y
Ni thickness (min)
 µm 2.5 2.5 2.5 2.5
Ni thickness (max)
 µm 5 5 5 5
Au thickness (min)
 µm 0.8 0.8 0.8 0.8
Au thickness (max)
 µm 5 5 5 5
immersion silver (Y/N) Y Y Y Y
immersion tin (Y/N) Y Y Y Y
OSP (Y/N) Y selective Y selective Y selective Y selective

 

summary technology roadmap units current production capability current prototype planned production capability planned prototype
SCREEN PRINT
peelable mask (Y/N) Y Y Y Y
carbon (Y/N) Y Y Y Y
via plugging (Y/N) Y Y Y Y
notation (legend) (Y/N) Y Y Y Y
notation - min line width µm 100 100 100 75
screen print notation registration capability (+/-) µm 100 75 100 75

 

summary technology roadmap units current production capability current prototype planned production capability planned prototype
PROFILE
rout min hole to edge (+/-) µm 130 100 100 80
scoring (V cut) location tolerance (+/-) µm 150 150 150 150
scoring (V cut) web thickness (1.6mm PCB) µm 500 500 500 500
scoring (V cut) web thickness tolerance (+/-) µm 100 100 100 100

 

summary technology roadmap units

current production capability

 current prototype planned production capability planned prototype
ELECTRICAL TEST
test voltage v 40 - 250 5 - 500 5 - 500 5 - 500
insulation requirements for shorts (max) MΩ 100 500 100 500
resistance for opens (mins)

Ω

 5 5 5 5
min pitch device (QFP)

µm

 300 200 300 150
min pitch device (array package) µm 300 300 300 300
max pad density text flying probe flying probe flying probe flying probe
interconnect stress test (IST) capability (Y/N) Y Y Y Y
buried capacitance testing F flying probe flying probe flying probe flying probe
absolute impedance (most difficult)

Ω

 50 50 50 50
min impedance tolerance  
single % 10 5 8 5
differential % 12 10 12 10

 
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